1. Technical Field
The present invention relates to digital circuits in general, and in particular to clock generation circuits. Still more particularly, the present invention relates to a clock generator having a deskewer.
2. Description of the Prior Art
A clock signal includes periodic transitions between a high and a low voltage levels at a rate typically described in terms of frequency, which is measured by the number of high/low transitions that occur per second. Within an integrated circuit, the timing of various digital logic circuits is typically controlled by one or more clock signals. The clock signals are utilized to synchronize bus cycles of the digital logic circuits. Hence, all digital logic circuits within the integrated circuit initiate data operations based upon the clock signals. More specifically, digital logic circuits change the state of their output signals in conjunction with the rising and/or falling edge of the clock signals.
Within an integrated circuit, clock signals are typically generated by a clock generator. Sometimes, when different digital logic circuits within an integrated circuit require clock signals of different frequencies, separate clock generators may be utilized to generate a clock signal of a specific frequency to cater the needs of the different digital logic circuits. When multiple clock generators are utilized to feed clock signals to different digital logic circuits within the integrated circuit, a difference in delay time may occur among the clock signal inputs to each of the digital logic circuits. This delay time is known as clock skew. Although clock skews are generally unavoidable because they can also be caused by many minute process variations occurred during fabrication, the present disclosure provides an improved clock generator with reduced clock skews.
In accordance with a preferred embodiment of the present invention, a clock generation circuit includes a waveform generator and a deskewer. Clocked by an input clock signal, the waveform generator generates a waveform signal. The deskewer circuit, which is connected to the waveform generator, gates the waveform signal from the waveform generator with the input clock signal to produce an output clock signal such that the output clock signal has less skew with respect to the input clock signal.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a block diagram of a first clock generation circuit according to the prior art;
FIG. 2 is a block diagram of a second clock generation circuit according to the prior art;
FIG. 3 is a block diagram of a clock generation circuit in accordance with a preferred embodiment of the present invention; and
FIG. 4 is a block diagram of a clock generation circuit in accordance with an alternative embodiment of the present invention.